The present invention pertains to the formation of vertical electrical interconnects within multiple layers of substrates, wherein a portion of the substrate layers are glass and a portion of the substrate layers are single-crystal silicon. Layers of other materials may be present as well. The invention is particularly advantageous in the fabrication of microcolumns, and especially an array of microcolumns of the kind used in electron optics, including electron microscopes and lithography apparatus.
As the size requirements for various electromechanical devices continue to diminish, there has been substantial interest in the manufacture of micro-electromechanical structures (MEMS). A typical MEMS structure incorporates at least one electrical device in combination with one or more mechanical device. Various attempts have been made to produce MEMS structures using common semiconductor processing techniques, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), and plasma etching. However, a typical MEMS structure is considerably larger than a typical semiconductor structure. The layers of materials used in a typical MEMS structure tend to be much thicker and cover a greater surface area than those used in conventional semiconductor devices. Therefore, depositing a layer of material using a CVD or PVD technique, or etching a material layer using plasma etching, can be too slow, such that the amount of time required to manufacture a MEMS structure using these techniques is prohibitive.
Many MEMS structures utilize various electronic devices etched out of silicon wafers. These electronic devices are then electrically isolated from each other by a layer of dielectric material. Recent work has focused on the use of glass sheets in lieu of dielectric layers which have been deposited using conventional semiconductor deposition techniques (which, as discussed above, are typically too slow to be practical for use in the deposition of dielectric layers of sufficient thickness for MEMS applications). Stacks of alternating layers of glass and conductive material (such as silicon) can be bonded together to produce various MEMS structures.
Anodic bonding has been one of the techniques used to bond the conductive layer to the glass layer. In some instances, a semiconductor material such as silicon is used as the conductive layer, and the glass layer is a borosilicate glass, such as PYREX(copyright) or BOROFLOAT(copyright) (Schott Glass Technologies, New York, N.Y.). In the alternative, the glass layer may be a lithium aluminosilicate-xcex2-quartz glass-ceramic, such as Prototype PS-100, available from HOYA Co., Tokyo, Japan. The advantage of this latter glass is that anodic bonding may be performed at a temperature of about 180xc2x0 C.
In order for the MEMS structure to function as a whole, it may be advantageous to form vertical electrical interconnects between the various conductive layers which have been electrically isolated from one another by sheets of glass. Because the interconnect is sealed within a multilayered sandwich and is difficult (if not impossible) to repair, it is important to obtain a robustness of these interconnects which is higher than wire bonding. A robust interconnect can be used in a harsh environment. To produce vertical electrical interconnects between conductive or semiconductive layers in a multilayered structure, there are a number of different possibilities, some of which are summarized below.
U.S. Pat. No. 4,525,766, issued Jun. 25, 1985, to Kurt E. Petersen, discloses a hermetically sealed electrical feedthrough conductor formed across the periphery or boundary between a hermetically sealed region on a semiconductor substrate and a second or external region thereof. A planar insulative layer is formed on the surface of the semiconductor (silicon) substrate along the predetermined path of the feedthrough conductor across the periphery of the insulative layer. The insulative layer has at least one planar projection on each side thereof which extends out to a point. Subsequently, a planar metal feedthrough conductor layer is applied which substantially covers the insulative layer, including planar projections. An insulator element sized to encapsulate the region to be sealed is then mallory bonded (anionic bonded) to the periphery, including the feedthrough conductor. The planar projections are said to form a compression bond that eliminates any tenting region that would otherwise form beneath the insulator element at the edges of the feedthrough conductor and the underlying insulative layer. The electrical feedthrough connections formed in this manner are generally in the same horizontal plane as the surface of the semiconductor substrate on which they are formed.
U.S. Pat. No. 5,584,956, issued Dec. 17, 1996, to Lumpp et al., describes a method for producing feedthroughs in a substrate having a front surface and a back surface. A sheet of material is bonded to the substrate using an adhesive. A laser is then used to form a hole through the substrate, where the laser radiation has a given wavelength at a power sufficient to ablate a hole through the substrate and a portion of the sheet behind the substrate, thereby creating a feedthrough in the substrate. The sheet of material may be conductive or an insulator. If the sheet is conductive, the sheet may remain bonded to the substrate to serve as a ground plane for the substrate. If the sheet is an insulator, the feedthrough is an insulated feedthrough, and if the sheet is conductive, the feedthrough is a conductive feedthrough. The procedure can be extended to produce a two-conductor feedthrough, where a wire is inserted, as illustrated in FIG. 6d, to produce a structure useful as a coaxial cable.
U.S. Pat. No. 5,656,553, issued Aug. 12, 1997, to Leas et al., illustrates a prior art approach to the problem of fabricating microcolumns of chips. As in other prior art, the assembly and subsequent contacting of the ICs in the stack is done after dicing of the chip or chip arrays out of the silicon wafers. In addition, the conductive interconnections disclosed can be said to be xe2x80x9cthree dimensionalxe2x80x9d only in the rather limited sense that xe2x80x9cside surface metallizationxe2x80x9d is applied to the peripheral edges of planar arrays of integrated chips subsequent to the dicing of the wafer.
In an article by R. De Reus et al. in Microelectronics Reliability (Vol. 38, pp. 1251-1260 (1998)), entitled xe2x80x9cReliability of Industrial Packaging For Microsystemsxe2x80x9d, the authors discuss packaging concepts for silicon-based micromachine sensors exposed to harsh environments. Various protective coatings of specialized materials, glue types, and thin-film anodic silicon-to-silicon wafer bonding processes are described. Through-hole electrical feedthroughs with a minimum line width of 20 xcexcm and a density of 250 wires per centimeter were obtained by applying electro-depositable photoresist. Hermetically sealed feedthroughs were obtained using glass frits, where the seal is said to withstand pressures of 4000 bar.
U.S. Pat. No. 5,998,292, issued Dec. 7, 1999, to Black et al., describes a method for interconnecting, through high-density micro-post wiring, multiple semiconductor wafers with lengths of about 1 millimeter or less. Specifically, the method comprises etching at least one hole, defined by walls, at least partly through a semiconductor material; forming a layer of electrically insulating material to cover the walls; and forming an electrically conductive material on the walls within the channel of the hole. The micro-post wiring may be used in devices of the kind described in the patent.
In an article by Xiaghua Li et al. entitled xe2x80x9cHigh density electrical feedthrough fabricated by deep reactive ion etching of Pyrex glassxe2x80x9d (Technical Digest, MEMS 2001, from the 14th IEEE International Conference on Micro Electro Mechanical Systems, pp. 98-101 (Jan 2001)), the authors describe a fabrication technology for producing PYREX(copyright) glass (manufactured by Corning Glass of Corning, N.Y.) with a fine pitch electrical feedthrough. Small through-holes (40-60 xcexcm in diameter) were fabricated using deep reactive ion etching in sulfur hexafluoride plasma. The through-holes were subsequently filled with nickel using pulse electroplating. The authors further comment that PYREX(copyright) glass can be anodically bonded with silicon, although they provide no example of the bonding process. Applications mentioned for use of the technology are micro-probe arrays used for high density data storage and packaged devices.
Within the field of integrated circuit (IC) fabrication, there is continuing interest in finding ways to increase the density of electronic parts such as transistors, and to shrink the electrical interconnections for these parts. Since the invention of microcolumns of silicon chips, only single columns have been assembled from a stack of micromachined silicon chips. In order to be able to contact each chip electrically, a stack of chips typically has a pyramidal structure. This allows wire bonding from each chip of the pyramid to a base plate through which electrical contact may be made. In the future, arrays of microcolumns will be needed. For the assembly of ten or more columns in an array, the pyramidal structure is not practical, depending on the required footprint and processing restrictions. In particular, monolithic designs of arrays require a different connection scheme than wire bonding. Therefore, there is a need for an electrically connected, multilayered structure which can be easily fabricated, without the limitations of a pyramidal structure.
We have developed a structure (and a method of forming the structure) which is used within a larger multilayered structure to transfer electrical signals vertically through the multilayered structure. The structure includes layers of glass which are anodically bonded to layers of conductive and/or semiconductive materials. The layers of glass act as a spacer, electrical isolator, and a soldering material between the conductive or semiconductive layers in the structure of the invention. At least a portion of the layers of glass within the structure include a through-hole, the interior surface of which is coated with an electrically conductive material which is sufficient to transfer electrical signals vertically through the glass layer in which they are present. Preferably, the conductive material is a metal which is evaporated through a shadow mask at an angle, or sputtered through a shadow mask, into the through-holes in the glass layer.
To prepare the openings through the glass layer, the openings may be ultrasonically drilled, wet chemically etched, or laser drilled, for example and not by way of limitation. Laser drilling has provided a smoother finish on the opening surfaces. It is also possible to plasma etch a pattern of openings into the oxide layer using SF6. The finish on the surface of an opening through silicon oxide is important, as this affects the ability of the conductive coating applied to form a continuous (pinhole-free) layer and to bond well to the silicon oxide surface. Preferably, the silicon oxide has a peak-to-peak surface roughness that is less than about 2 xcexcm.
During deposition of a metal coating on the interior surfaces of the through-hole, the glass layer containing the through-hole may be rotated to obtain a uniform metal coating on the inside surface of the through-hole. The coating is applied not only to the interior of the through-hole, but is also extended onto each surface of a glass plate in the area surrounding the through-hole. The thickness of the conductive coating on the surface of the glass plate should be less than about 300 nm when the glass plate is to be anodically bonded to a silicon plate. The minimum conductive coating thickness required depends on the roughness of the interior surface of the through-hole. In general, when the through-hole surface is relatively rough, a thicker conductive coating is needed than when the through-hole has a smoother interior surface. For example, when the surface roughness of the through-hole is about 200 nm, a conductive coating having a minimum thickness of 200 nm should be applied; when the surface roughness is about 50 nm, a minimum conductive coating thickness of 50 nm should be applied.
In one embodiment of the invention, the glass layer is attached to, preferably bonded to, a semiconductor layer prior to application of the conductive material to the through-hole surface. In this embodiment, one end of the through-hole, which is covered by the semiconductor layer, is also coated with the conductive material. Subsequent to deposition of the metal coating on the interior surfaces of the glass layer through-hole, with preferable simultaneous deposition on the surface of a semiconductor material covering one end of the glass through-hole, the glass layer is anodically bonded to at least one conductive layer or to a semiconductor layer.
The present invention avoids the requirement of a pyramidal structure by implementation of robust electrical feedthroughs within a multilayered substrate which can be diced to provide desired device structures.
Accordingly, disclosed herein is a method of preparing a vertical, electrically connected substrate structure. The method includes the steps of: a) providing a second substrate overlying a first substrate, wherein the first substrate and the second substrate comprise materials having similar coefficients of expansion, and wherein the second substrate has at least one through-hole formed therein; b) anodically bonding the first substrate to the a first surface of the second substrate; c) simultaneously depositing a layer of a conductive material over an interior surface of the at least one through-hole, an upper portion of the first substrate exposed in the area of the through-hole, and over a portion of a second surface of the second substrate surrounding the through-hole, thereby forming a conductive pad surrounding the through-hole; and d) anodically bonding a third substrate to the second surface of the second substrate, wherein the second substrate and the third substrate comprise materials having similar coefficients of expansion, whereby the first substrate is electrically connected to the third substrate by means of the conductive material layer.
Another embodiment, in which a glass layer is sandwiched between two semiconductor layers and it is desired to use a thick conductive coating which would interfere with anodic bonding of the glass to semiconductor surfaces, is described below. In this embodiment, the glass layer may extend beyond the semiconductor layers to which it is bonded, such that the opening in the glass layer extends beyond the opening in the semiconductor layer. This enables the application of a thick conductive coating on the surface of the glass opening without affecting anodic bonding between the glass and semiconductor layers.
Also disclosed herein is a second embodiment method of preparing a vertical, electrically connected substrate structure, comprising the following steps: a) providing a second substrate overlying a first substrate, wherein the first substrate and the second substrate comprise materials having similar coefficients of expansion, wherein the first substrate has at least one through-hole formed therein, and the second substrate has at least one through-hole formed therein, wherein a diameter of the first substrate through-hole is larger than a diameter of the second substrate through-hole, and wherein the first substrate through-hole is in communication with the second substrate through-hole; b) anodically bonding the first substrate to the second substrate; c) depositing a first layer of a conductive material over an interior surface of the second substrate through-hole and over a portion of an upper surface of the second substrate; d) depositing a second layer of the conductive material over an interior surface of the second substrate through-hole and over a portion of an upper surface of the second substrate, wherein the upper surface portion which is covered by the second conductive material layer is less than the upper surface portion which is covered by the first conductive material layer; and e) depositing a third layer of the conductive material over an interior surface of the first substrate through-hole, an interior surface of the second substrate through-hole, and over a portion of a lower surface of the second substrate. This embodiment of the invention is particularly useful when a conductive material coating having a thickness greater than 300 nm is required.
The above method can be used to prepare basic xe2x80x9cunitsxe2x80x9d which can be stacked and anodically bonded together to form an electrically connected, multi-unit substrate structure. In this case, the above method further includes the following steps: f) providing a second substrate structure which has the same structure as the first substrate structure, and is formed by the same process as the first substrate structure; g) aligning the second substrate structure with the first substrate structure such that the first substrate of the second substrate structure is in contact with the second substrate of the first substrate structure; and h) anodically bonding the second substrate structure to the first substrate structure, whereby the first substrate structure is electrically connected to the second substrate structure by means of the conductive material layers, and whereby all substrates in the first and second substrate structures are electrically connected.
An alternative embodiment of the above method includes only two conductive material layer deposition steps (i.e., the step d) conductive material layer deposition step of the above embodiment is omitted). This embodiment comprises the following steps: a) providing a second substrate overlying a first substrate, wherein the first substrate and the second substrate comprise materials having similar coefficients of expansion, wherein the first substrate has at least one through-hole formed therein, and the second substrate has at least one through-hole formed therein, wherein a diameter of the first substrate through-hole is larger than a diameter of the second substrate through-hole, and wherein the first substrate through-hole is in communication with the second substrate through-hole; b) anodically bonding the first substrate to the second substrate to form a first substrate structure; c) depositing a first layer of a conductive material over an interior surface of the second substrate through-hole and over a portion of an upper surface of the second substrate; and d) depositing a second layer of the conductive material over an interior surface of the first substrate through-hole, an interior surface of the second substrate through-hole, and over a portion of a lower surface of the second substrate. This embodiment is particularly useful for use with glass through-holes having an aspect ratio of 2:1 or less. As used herein, the term xe2x80x9caspect ratioxe2x80x9d refers to the ratio of the thickness of the glass layer (i.e., the xe2x80x9cheightxe2x80x9d of the through-hole) to the diameter of the through-hole. If the aspect ratio of the through-hole is too high, it may be difficult to entirely coat the surface of the through-hole with metal.
The above method can also be used to prepare basic xe2x80x9cunitsxe2x80x9d which can be stacked and anodically bonded together to form an electrically connected, multi-unit substrate structure. In this case, the above method further includes the following steps: e) providing a second substrate structure which has the same structure as the first substrate structure, and is formed by the same process as the first substrate structure; f) aligning the second substrate structure with the first substrate structure such that the first substrate of the second substrate structure is in contact with the second substrate of the first substrate structure; and g) anodically bonding the second substrate structure to the first substrate structure, whereby the first substrate structure is electrically connected to the second substrate structure by means of the conductive material layers, and whereby all substrates in the first and second substrate structures are electrically connected.
Another embodiment of the method of the invention for preparing a vertical, electrically connected substrate structure includes the following steps: a) providing a second substrate sandwiched between a first substrate and a third substrate, wherein the first substrate, the second substrate, and the third substrate comprise materials having similar coefficients of expansion, wherein the first substrate, the second substrate, and the third substrate each has at least one through-hole formed therein, and wherein a diameter of the first substrate through-hole and a diameter of the third substrate through-hole are larger than a diameter of the second substrate through-hole, and wherein the first substrate through-hole is in communication with the second substrate through-hole, and the second substrate through-hole is in communication with the third substrate through-hole; b) anodically bonding the second substrate to the first substrate and the third substrate; c) depositing a first layer of a conductive material over an interior surface of the third substrate through-hole, a portion of an upper surface of the second substrate, and an interior surface of the second substrate; and d) depositing a second layer of a conductive material over an interior surface of the first substrate through-hole, a portion of a lower surface of the second substrate, and an interior surface of the second substrate through-hole.
Yet another embodiment of the method of the invention comprises the following steps: a) providing a first substrate, wherein the first substrate has at least one through-hole formed therein; b) depositing a first layer of a conductive material over a portion of an upper surface of the first substrate and over an interior surface of the first substrate through-hole; c) depositing a second layer of a conductive material over a portion of an upper surface of the first substrate and over an interior surface of the first substrate through-hole, wherein the upper surface portion which is covered by the second conductive material layer is less than the upper surface portion which is covered by the first conductive material layer; d) depositing a third layer of a conductive material over a portion of a lower surface of the first substrate and over an interior surface of the first substrate through-hole; and e) depositing a fourth layer of a conductive material over a portion of a lower surface of the first substrate and over an interior surface of the first substrate through-hole, wherein the lower surface portion which is covered by the fourth conductive material layer is less than the upper surface portion which is covered by the third conductive material layer. Preferably, the first substrate is then sandwiched between and anodically bonded to a second substrate and a third substrate, where the second substrate and the third substrate comprise materials having a similar coefficient of expansion as the first substrate.
Another method of preparing a vertical, electrically connected substrate structure comprises the steps of: a) providing a second substrate overlying a first substrate, wherein the first substrate and the second substrate comprise materials having similar coefficients of expansion, wherein the first substrate has at least one through-hole formed therein, and the second substrate has at least one through-hole formed therein, wherein a diameter of the first substrate through-hole is smaller than a diameter of the second substrate through-hole, and wherein the first substrate through-hole is in communication with the second substrate through-hole; b) anodically bonding the first substrate to the second substrate; and c) depositing a first layer of a conductive material over a portion of an upper surface of the second substrate, an interior surface of the second substrate through-hole, a portion of an upper surface of the first substrate, and an interior surface of the first substrate through-hole. The above method can also be used to prepare basic xe2x80x9cunitsxe2x80x9d which can be stacked and anodically bonded together to form an electrically connected, multi-unit substrate structure, as described above.